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TMP90C041
2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions are described below.
2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90C041N.
Figure 2.1-(1). Pin Assignment (Shrink Dual Inline Package)
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Figure 2.1 (2) shows pin assignment of the TMP90C041F.
Figure 2.1 (2). Pin Assignment (Flat Package) 2.2 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
D0 ~ D7 A0 ~ A7 A8 ~ A15 P30 /RxD P31 /RxD P32 /TxD /RTS /SCLK P33 /TxD P34 /CTS RD WR P37 /WAIT
No. of pins
8 8 8 1
I/O 3 states
3 states Output Output Input
Function
Data bus: Also functions as 8-bit bidirectional data bus for external memory Address bus: The lower 8 bits address bus for external memory Address bus: The upper 8 bits address bus for external memory Port 30: 1-bit input port Receiver Serial Data Port 31: 1-bit input port Receiver Serial Data Port 32: 1-bit input port
1
Input
1
Output
Transmitter Serial Data Request to send Serial Data Serial clock output
1
Output
Port 33: 1-bit output port Transmitter Serial Data Port 34: 1-bit input port Clear to send Serial Data Read: Generates strobe signal for reading external memory Write: Generates strobe signal for writing into external memory Port 37: 1-bit input port Wait: Input pin for connecting slow speed memory or peripheral LSI
1 1 1 1
Input Output Output Input
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Table 2.2 Pin Names and Functions (2/2)
Pin Name
P40 ~ P43 /A16 ~ A19 P50 ~ P55 /AN0 ~ AN5 VREF AGND P60 ~ P63 /M00 ~ M03 /TO1 P70 ~ P73 /M10 ~ M13 /TO3
No. of Pins
4
I/O 3 states
Output
Function
Port 4: 4-bit output port that allows selection of Port/Address Bus on bit basis Address bus: Also functions as address bus for external memory (4 bits of bank address) Port 5: 6-bit input port Analog input: 6 analog input to A/D converter Input of reference voltage to A/D converter Ground pin for A/D converter Port 6: 4-bit I/O port that allows I/O selection on bit basis Stepping motor control port 0 Timer output 1: Output of Timer 0 or 1 Port 7: 4-bit I/O port that allows I/O selection on bit basis Stepping motor control port 1 Timer output 3: Output of Timer 2 or 3 Port 80: 1-bit input port
6 1 1
Input - - I/O
4
Output Output I/O
4
Output Output
P80 /INTO
1
Input
Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
Port 81: 1-bit input port P81 /INT1 /TI4 Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable)
1
Input
Timer input 4: Counter/capture trigger signal for Timer 4 P82 /INT2 /TI5 P83 /TO3/T04 NMI Port 82: 1-bit input port 1 Input Interrupt request pin 2: rising edge interrupt request pin Timer input 5: capture trigger signal for Timer 4 1 Output Port 83: 1-bit output port Timer output 3/4: Output of Timer 2, 3 or 4 Non-maskable interrupt request pin: Falling edge interrupt request pin 1 Input Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up internally during resetting. External access: Connects with GND pin in the TMP90C041 with no internal ROM. Reset: Initializes the TMP90C041. (Built-in pull-up resistor) Pin for quartz crystal or ceramic resonator Power supply (+5V) Ground (0V)
CLK EA RESET X1/X2 VCC VSS (GND)
1 1 1 2 1 1
Output Input Input Input/ Output - -
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3. Operation
The following explains the TMP90C041 functions and basic operations. The CPU functions and internal I/O functions of the TMP90C041 are the same as the TMP90C840A. Refer to the "TMP90C840A" section concerning functions which are not explained in the following. 3.1 CPU The TMP90C041 has an internal high-performance 8-bit CPU. Refer to the book TLCS Series CPU Core Architecture concerning CPU operation.
3.2 Memory Map The TMP90C041 supports a program memory of up to 64K bytes and a data memory of maximum 1M bytes. The program memory may be assigned to the address space from 00000H to 0FFFFH, while the data memory can be allocated to any address from 00000H to FFFFFH. (1) Internal I/O The TMP90C041 provides a 48-byte address space as an internal I/O area, whose addresses range from FFC0H to FFEFH. This I/O area can be accessed by the CPU using a short opcode in the "direct addressing mode". Figure 3.1 is a memory map indicating the areas accessible by the CPU in the respective addressing
mode.
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Figure 3.2. Memory Map
4. Electrical Characteristics
TMP90C041N/TMP90C041F 4.1 Absolute Maximum Ratings
Symbol
VCC VIN PD TSOLDER TSTG TOPR Supply voltage Input voltage Power dissipation (Ta = 70C) Soldering temperature (10s) Storage temperature Operating temperature
Parameter
Rating
-0.5 ~ + 7 -0.5 ~ VCC + 0.5 F 500 N 600 260 -65 ~ 150 -20 ~ 70
Unit
V V mW C C C
4.2 DC Characteristics
TA = -20 ~ 70C VCC = 5V 10% Typical Values are for TA = 25C and VCC = 5V. Symbol
VIL VIL1 VIL2 VIL4 VIH VIH1 VIH2 VIH4 VOL VOH VOH1 VOH2 IDAR ILI ILO
Parameter
Input Low Voltage (D0 ~ D7) P3, P5, P6, P7, P8 RESET, INT0, NMI X1 Input Low Voltage (D0 ~ D7) P3, P5, P6, P7, P8 RESET, INT0, NMI X1 Output Low Voltage Output High Voltage Darlington Drive Current (8 I/O pins) Input Leakage Current Output Leakage Current Operating Current (RUN) Idle 1 Idle 2 STOP (TA = -20 ~ 70C) STOP (TA = 0 ~ 50C)
Min
-0.3 -0.3 -0.3 -0.3 0.2VCC + 1.1 0.7VCC 0.75VCC 0.8VCC - 2.4 0.75VCC 0.9VCC -1.0 0.02 (Typ) 0.05 (Typ) 20 (Typ) 1.5 (Typ) 9 (Typ) 0.2 (Typ) 50 - 0.4
Max
0.2VCC - 0.1 0.3VCC 0.25VCC 0.2VCC VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.45 -
Unit
V V V V V V V V V V V V mA A A mA mA mA A A K pF V
Test Conditions
- - - - - - - - IOL = 1.6mA IOH = -400A IOH = -100A IOH = -20A VEXT = 1.5V REXT = 1.1k 0.0 Vin VCC 0.2 Vin VCC - 0.2 tosc = 12.5MHz 0.2 Vin VCC - 0.2 - testfreq = 1MHz -
-3.5 5 10 40 5 15 50 10 150 10 1.0 (Typ)
ICC
RRST CIO VTH
RESET Pull Up Register Pin Capacitance Schmitt width RESET, NMI, INT0
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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4.3 AC Characteristics
TA = -20 ~ 70C VCC = 5V 10% CL = 50pF Variable Symbol
tOSC tCYC tWL tWH tAC tRR tCA tAD tRD tHR tWW tDW tWD tCWA tAWA tWAS tWAH tRV tCPW tPRC tCPR tCHCL tCLC tCLHA tACL tCLD OSC. Period = x CLK Period CLK Low width CLK High width Address Setup to RD, WR RD Low width Address Hold Time After RD, WR Address to Valid Data In RD to Valid Data In Input Data Hold After RD WR Low width Data Setup to WR Data Hold After WR RD, WR to Valid WAIT Address to Valid WAIT WAIT Setup to CLK WAIT Hold After CLK RD/WR Recovery Time CLK to Port Data Output Port Data Setup to CLK Port Data Hold After CLK RD/WR Hold After CLK RD/WR Setup to CLK Address Hold After CLK Address Setup to CLK Data Setup to CLK
10MHz Clock Max
1000 4x - - - - -
12.5MHz Clock Unit Min
80 320 120 120 35 160 10 - - 0 160 110 30 - - 70 0 85 - 200 100 20 70 40 120 30
Parameter Min
80 4x 2x - 40 2x - 40 x - 45 2.5x - 40 0.5x - 30 0 2.5x - 40 2x - 50 30 - - 70 0 1.5x - 35 - 200 100 x-60 1.5x - 25 1.5x - 80 2.5x - 80 x - 50
Min
100 400 160 160 55 210 20 - - 0 210 150 30 - - 70 0 115 - 200 100 40 100 70 170 50
Max
- - - - - - 255 170 - - - 90 50 120 - - - 300 - - - - - - -
Max
- - - - - - - 185 120 - - - 90 20 70 - - - 280 - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.5x - 95 2.5x - 80 - - - 90 1.5x - 100 2.5x - 130 - - - x + 200 - - - - - - -
* AC output level High 2.2V/Low 0.8V * AC input level High 2.4V/Low 0.45V (D0 - D7) High 0.8VCC/Low 0.2VCC (excluding D0 - D7)
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4.4 A/D Conversion Characteristics
TA = -20 ~ 70C VCC = 5V 10% Symbol
VREF AGND VAIN IREF Error Analog reference voltage Analog reference voltage Allowable analog input voltage Supply current for analog reference voltage Total error (TA = 25C, VCC = VREF = 5.0V) Total error
Parameter
Min
VCC - 1.5 VSS VSS - - -
Typ
VCC VSS - 0.5 - -
Max
VCC VSS VCC 1.0 1.0 2.5
Unit
V
mA LSB
4.5 Zero-Cross Characteristics
TA = -20 ~ 70C VCC = 5V 10% Symbol
VZX AZX FZX
Parameter
Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency
Condition
AC coupling C = 0.1F 50/60Hz sine wave -
Min
1 - 0.04
Max
1.8 135 1
Unit
VAC p - p mV kHz
4.6 Serial Channel Timing-I/O Interface Mode
TA = -20 ~ 70C VCC = 5V 10% CL = 50pF Variable Symbol
tSCY tOSS tOHS tHSR tSRD
10MHz Clock Max
- - - -
12.5MHz Clock Unit Min
640 330 40 0 -
Parameter Min
Serial Port Clock Cycle Time Output Data Setup SCLK Rising Edge Output Data Hold After SCLK Rising Edge Input Data Hold After SCLK Rising Edge SCLK Rising Edge to Input DATA Valid 8x 6x - 150 2x - 120 0 -
Min
800 450 80 0 -
Max
- - - - 450
Max
- - - - 330 ns ns ns ns ns
6x - 150
4.7 16-bit Event Counter
TA = -20 ~ 70C VCC = 5V 10% Variable Symbol
tVCK tVCKL tVCKH TI4 clock cycle TI4 Low clock pulse width TI4 High clock pulse width
10MHz Clock Max
- - -
12.5MHz Clock Unit Min
740 360 360
Parameter Min
8x + 100 4x + 40 4x + 40
Min
900 440 440
Max
- - -
Max
- - - ns ns ns
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4.8 Interrupt Operation
TA = -20 ~ 70C VCC = 5V 10% Variable Symbol Parameter Min
NMI, INT0 Low level pulse width tINTAL NMI, INT0 High level pulse width tINTAH INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 8x + 100 - 900 - 740 - ns 8x + 100 - 900 - 740 - ns 4x - 400 - 320 - ns 4x - 400 - 320 - ns
10MHz Clock Max Min Max
12.5MHz Clock Unit Min Max
(Reference) Definition of IDAR
4.9 I/O Interface Mode Timing Chart
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4.10 Timing Chart
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5. Differences Between TMP90C841A and TMP90C041
Specifications of TMP90C841A and TMP90C041 are the same except below. TMP90C841A system, not using internal RAM and
internal I/O functions as shown below, can be substituted by TMP90C041 system. To substitute the TMP90C841A system using the internal RAM by the TMP90C041 system, it is necessary to attach the external RAM to the address corresponded to the internal address.
Name
RAM A0 ~ A15 P0 (0FFC1H) P1 (0FFC1H) P2 (0FFC4H) P01CR (0FFC2H) P2CR (0FFC5H)
TMP90C841A
256 bytes of internal RAM are provided. (0FEC0H ~ 0FFBFH) High-Impedance state during reset Provided (same chip as TMP90C840A) Provided Provided External memory area. Driving state during reset. R/W function is not provided.
TMP90C041
EXT, P1C, P0C is not provided. P2XC register is not provided
* Note: Connect EA pin with GND pin.
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